The preferred embodiments relate to boundary scan of integrated circuits and printed circuit boards.
Boundary scan is a method and related circuiting for testing logic, memories, and other circuits on an integrated circuit (IC) or printed circuit board (PCB). Typically for boundary scan, four or five pins are included on an IC, each corresponding to a respective dedicated test access port (TAP) signal for testing interconnects on either the IC or a PCB into which the IC is assembled. Specifically, the TAP signals may be used to determine whether an IC is properly functioning, whether it is connected to the PCB, and also for debugging by observing IC pin states or measured voltages. Testing may be achieved at the time of manufacture, such as by automated testing equipment (ATE), as well as subsequent testing in the field (e.g., once a device has been sold or located in the marketplace). Additional details as well as standardization in connection with boundary scan were developed by the Joint Test Action Group (JTAG) and are specified in an IEEE 1149 standard and its .x sub-standards.
By way of further background, FIG. 1 illustrates an electrical block diagram of an IC 10 having a boundary scan architecture according to the prior art. For purposes of simplifications, IC 10 is shown to include a test access port TAP controller 12 for interfacing with TAP signals and as relating to JTAG testing, as well as IC functional circuitry 14, sometimes referred to as a core, which is a general depiction of the various circuit functions of IC 10, apart from JTAG testing. IC 10 also includes a number of I/O pads P0 through P15, shown at various locations around the perimeter of the device. Pads P0 through P4 carry respective and known JTAG TAP related signals, as shows In the following Table 1.
TABLE 1PinJTAG SignalFunctionP0TDOtest data outP1TRSTtest resetP2TMStest mode selectP3TCKtest clockP4TDItest data inAs indicated in Table 1, pad P4 allows input of JTAG test data and pad P0 allows output thereof, while the remaining pads P1 through P3 provide signals to TAP controller 12. An instruction register 16 stores a current JTAG instruction, typically to indicate the operation to take with respect to signals that are received (e.g., defining to which data register signals should pass). A bypass register 18 is a single bit register that permits TDI to bypass a chain of cells C0 through C15 so as to pass directly from input to output. An ID register 20 is for storing the ID code and revision number for IC 10, thereby allowing IC 10 to be linked to a file that stores boundary scan configuration information for IC 10.
Apart from the JTAG-related pads P0 through P4, each of the remaining IC pads P5 through P15 is connected through a respective boundary scan cell C5 through C15, to functional circuitry 14. Thus, such pads represent the I/O of IC 10, in connection with its intended operation as achieved by functional circuitry 14. In addition, however, and in connection with JTAG testing, each of scan cells C5 through C15 is connected to at least one other scan cell, thereby forming a scan chain whereby for JTAG purposes data may be input by a respective pad to each cell, or captured in each cell from functional circuitry 14, and then such data may be successively shifted along the chain so that it is output from the last such cell C15 as TDO information. In this manner, therefore, the I/O connectivity as well as data states from functional circuitry 14 may be evaluated so as to confirm proper operation of IC 10.
While the preceding has proven effective in IC and PCB testing across numerous architectures, the IEEE 1149.x standard requires that the JTAG pads themselves are not connected to respective scan cells and accordingly by way of example in FIG. 1 pads P0 through P4 are not connected to such respective cells. Such a mandate, however, provides limitations as improved by the preferred embodiments, as further detailed below.